Testability VLSI: Boundry scan
- Boundary scan is a test technique using scan methodology, involving digital services, digital devices, designed with shift registers (scan flip flops) placed between each devicepin and the internal logic.
- These shift registers can control and observe signal values present at each input and output pin and are connected together in serial fashion to form a data register chain, called boundary scan shift register with shift and update stages.
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| Testability VLSI: Boundary scan |
· The update stage latch prevents
output from rippling as data is shifted through the shift
register during scan operation Fig.
9.10.1 shows how the boundary scan registers can be
connected in an ASIC.
· Test sets generated by ATPG can be
scanned into these boundary scan registers through
scan in port such that test stimuli
are applied parallel, circuit response can be captured in
parallel by boundary scan registers
connected between internal logic and output pins and
scanned out through scan out port.
Read also:
JTAG Testability: JTAG Test Access Port Controller
Testability VLSI: Boundary scan video:
Read also:
JTAG Testability: JTAG Test Access Port Controller
Testability VLSI: Boundary scan video: