JTAG Test Access Port
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| JTAG Testability: JTAG Test Access Port Controller |
The TAP is a general-purpose port that can provide access to many test support functions built into a component, including the test logic defined by this standard.
It is composed as a minimum of the three input connections and one output connection required by the test logic defined by this standard. An optional fourth input connection provides for asynchronous initialization of the test logic defined by this standard.
The JTAG Test Access Port consists of four pins that drive the circuit blocks. The four pins, 'FMS, TCK, TDI and TDO.
TCK
(Test Clock Input) : This pin sequences the TAP controller of the JTAG
registers.
TMS
(Test Mode Select Input) : This pin is the mode input signal that provides
the control logic for JTAG.
TIM
(Test Data Input) : This pin is the serial data input to all JTAG instruction
and data registers.
TDO
(Test Data Output) : This pin is the serial data output for all JTAG
instruction and data registers.
JTAG TAP Controller :
The TAP controller is a finite state machine that responds to changes at the TMS and TCK signals of the TAP and controls the sequence of operations of the circuitry defined by standard.
The JTAG TAP Controller is a finite state machine, which controls the scanning of data into the various registers of the JTAG architecture.
Two state transition paths for scanning the signal at TDI, one for shifting to the
instruction register and one for
shifting data into the active data register.
JTAG TAP Controller States
:
The state diagram for the TAP
controller. Transitions of the TAP controller shall occur based on the value of
TMS at the time of a
rising edge of TCK.
Actions of the test logic
(instruction register, test data registers, etc.) shall occur on either the rising or the falling
edge of TCK in each controller state.